ASIC Design - Front-End
The company has a large team of experienced engineers in UVM, System Verilog and eSpecman at IP and SoC level. For further details please visit Functional Design Verification.
ASIC Design - Back-End
All the flow: Silicon Service provides services for RTL to GDSII, Logic Synthesis, Place & Route, STA and Verification at IP level.
Logic Synthesis is one of the earliest capabilities in Silicon Service. Over the time, experience has accumulated through different synthesis tools.
Place and Route experience with different package tools includes signal integrity checks like voltage drop, electromigation or crossTalk.