Functional Design Verification

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Functional Design Verification

Digital design verification represents around 95% of our capacity and expertise. Our engineers have a thorough competence in the latest design verification technologies and legacy tools/flows that can be used by our clients:

  • SV/UVM, OVM, C/C++, ASM
  • Architectures: ARM, x86
  • I/O Protocols: AMBA, PCIe, Ethernet, DDR, SerDes, I2C, SPI
  • SoC, GPU, Performance, Security,
  • Low-Power Verification & UPF

The main core of outsourcing services consists of a large team of design verification engineers (UVM, System Verilog and eSpecman) with IP and x86/arm SoC level verification experience.

IP Level Verification Expertize:

  • Experienced in Power management, Fuse and DFX IPs for x64 architecture
  • OVM/UVM, System Verilog, C/C++, erm, Specman, scripting languages
  • Write test plans, creating/updating/integrating verification environments, writing monitors, checkers, scoreboard, adding and analyzing coverage, writing and maintaining stimulus and tests, debugging and fix bugs.

Functional Design Verification Services, SoC Level Expertise:

  • IP integration and bringup
  • Debug and Fix Verification, Test or RTL Issues
  • Power Management/ Low power / Power Gating/DDR
  • OVM/UVM Skills
  • Writing testcases, test-benches, random stimulus, sequences, coverage collection and review
  • Emulator bringup, debug and support

Interested in Our Functional Design Verification Services?